The fabrication of semiconductor devices has progressed significantly over the last four decades. Semiconductor chips incorporating over a million transistors are possible. However, the development of technologies such as interactive high-definition television, personal global communications systems, virtual reality applications, real-life graphics animation, and other scientific and industrial applications, will demand higher speed, more functionality, and further advances in very large scale integration technology. The demand for more functionality will require an increase in the number of transistors that need to be integrated on a chip. This will require shrinking the area required to fabricate interconnected transistors, or will require larger die sizes, or both. As the feature size decreases, and the area required to fabricate transistors decreases, the resulting increased density of devices will require an increasing number of interconnections within a chip, or interconnections between chips in a multi-chip design.
Transistors or gates typically make up a circuit cell. Each cell of an integrated circuit includes a plurality of points, sometimes referred to as pins or terminals, each of which must be connected to pins of other cells by an electrical interconnect wire network or net. Cells may comprise individual logic gates, or more preferably may each comprise a plurality of logic gates or transistors that are interconnected to form functional blocks. It is desirable to attempt to optimize a design so that the total wirelength and interconnect congestion are minimized.
As the number of transistors on a single chip becomes very large, gains made in reducing the feature size brought on by advances in fabrication technology may be offset by the increased area required for interconnection. As the number of interconnections increase, the amount of real estate on the semiconductor die occupied by interconnections could become relatively large unless steps are taken to improve conventional layout techniques.
It is desirable to achieve minimum area layouts for very large scale integration circuits, because minimum area layouts typically deliver optimum performance and provide the most economical implementation of a circuit. It is therefore desirable to have an architecture that will minimize the area occupied by the active part of the circuit. For example, an architecture that will tile well may provide advantages in minimizing the area occupied by the active part of the circuit. It is also desirable to have an architecture that will minimize the area occupied by the passive part of the circuit, i.e., the interconnection. This may be achieved by an architecture that provides better routing options. Ultimately, the theoretical lower limit on minimizing the area occupied by the interconnections is a zero-routing footprint chip.
In the early days of large scale integration, only a single layer of metal was available for routing, and polysilicon (polycrystalline silicon) and a single such metal layer were used to complete the interconnections. The first metal layer may be referred to as the "metal 1" layer or "M1" layer. As semiconductor fabrication processes improved, a second metal layer was added. The second metal layer may be referred to as the "metal 2" layer or "M2" layer. A rectangular approach to routing was used to determine the location of interconnections. Fabrication processes have now been developed which provide three or four metal layers. Fabrication processes which provide five or more metal layers are also being developed. Conductors can be formed in layers that are electrically insulated from the cells and extend over the cells, in what is sometimes referred to as over-the-cell routing. With three or four metal layers available for routing, it may be possible to approach a chip containing no area set aside exclusively for routing (i.e., a zero-routing footprint chip) if over-the-cell routing is utilized.
The performance of a chip depends on the maximum wire length of the interconnection metal used. For better performance, it is desirable to minimize the maximum wire length. As the feature size is made smaller, the delay per unit length of interconnection increases. According to one reference, a 7 micron NMOS technology may have a per unit resistance of 21 ohms per centimeter; and by comparison, a 0.35 micron CMOS technology may have a per unit resistance of 2440 ohms per centimeter. See N. Sherwani, S. Bhingarde & A. Panyam, Routing in the Third Dimension, at 8 (1995), the entirety of which is incorporated herein by reference.
The performance of a chip is bound by the time required for computation by the logic devices and the time required for the data communication. In the past, the time required for data communication was typically insignificant compared to the time required for computation, and could be neglected. In the past three decades, there has been a significant improvement in the average speed of computation time per gate. Now, the interconnection delays are on the order of gate delays and as a result, have become significant and can no longer be ignored. Interconnect delays are an increasing percentage of path delay.
When two points are interconnected by metal, a connection is formed which may be referred to as a wire. When two wires in the same metal layer run parallel to each other, parasitic capacitances may be significant and "crosstalk" may occur between signals on those wires. The metal 1 layer is typically separated from the metal 2 layer by a dielectric. When only two metal layers were used, a rectangular or rectilinear approach to routing provided metal 1 wires at 90 degrees relative to metal 2 wires, and this gave satisfactory results in many instances. However, a rectangular approach to routing when three metal layers are available has provided metal 3 wires parallel to metal 1 wires, and these metal layers are separated by layers of dielectric. This has resulted in unsatisfactory capacitance and "crosstalk" in many instances. With four metal layers, metal layers M1 and M3 may have parallel wires, and metal layers M2 and M4 may have parallel wires. Significant performance degradation may result. In the past, efforts to increase the number of metal layers in an attempt to approach a zero-routing footprint chip have resulted in offsetting performance degradation due to unsatisfactory capacitance and "crosstalk" from parallel wires located in different metal layers.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
Typically, the layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns by an optical or electron beam pattern generator that are called masks.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. This component formation requires very exacting details about geometric patterns and separation between them. These details are expressed by a complex set of design rules. The process of converting the specifications of an electrical circuit into a layout is called the physical design. It is an extremely tedious and an error-prone process because of the tight tolerance requirements, the complexity of the design rules, and the minuteness of the individual components.
Currently, the geometric feature size of a component may be as small as on the order of 0.5 microns. However, it is expected that the feature size can be reduced to 0.1 micron within several years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
As stated above, each microelectronic circuit cell includes a plurality of pins or terminals, each of which must be connected to pins of other cells by a respective electrical interconnect wire network or net. A goal of the optimization process is to determine a cell placement such that all of the required interconnects can be made, and the total wirelength and interconnect congestion are minimized. A goal of routing is to minimize the total wirelength of the interconnects, and also to minimize routing congestion. Achievement of this goal is restricted using conventional rectilinear routing because diagonal connections are not possible. Rarely are points to be connected located in positions relative to each other such that a single straight wire segment can be used to interconnect the points. Typically, a series of wire segments extending in orthogonal directions have been used to interconnect points. A diagonal path between two terminals is shorter than two rectilinear orthogonal paths that would be required to accomplish the same connection. Another drawback of conventional rectilinear interconnect routing is its sensitivity to parasitic capacitance. Since many conductors run in the same direction in parallel with each other, adjacent conductors form parasitic capacitances that can create signal crosstalk and other undesirable effects.
Conventional memory arrays such as DRAMs and SRAMs have been density limited by the metal pitch, which has become a limiting feature inhibiting further shrinkage of the size of the layout. In a conventional two layer memory array, the bit lines and the select lines normally run on the same level of metal. As a result, as memory layouts are made smaller and smaller, the bit lines and the select lines become closely packed. Wiring congestion, crosstalk, and parasitic capacitance are problems limiting the performance and size of conventional memory arrays.
In the case of a DRAM cell, in particular, the line capacitance can be a problem when it becomes large relative to the storage capacitance of the cell storage devices. A DRAM memory circuit can only tolerate a certain ratio of line capacitance to storage capacitance. Conventional designs are limited in the available options to deal with this problem. Attempts have been made to adjust the ratio of storage capacitance to line capacitance by increasing the storage capacitance. However, increasing the cell size tends to increase the size of the layout on a die, and limits the amount of circuitry that can be laid out on a given size die, and may inflict performance penalties. Large amounts of storage capacitance may slow the speed of a memory array. Large amounts of capacitance take longer to charge and discharge because larger capacitance has larger RC time constants. This slows the operation of the memory circuit. The speed of microprocessors and other circuits has become so fast that memory accesses can be a significant limitation upon the performance of a system where access speeds measured in nanoseconds are considered to be slow. Thus, increased capacitance can be a problem with high performance memory circuits.
As illustrated in FIG. 1, a conventional microelectronic integrated circuit 93 comprises a substrate 95 on which a large number of semiconductor devices are formed. These devices include large functional macroblocks such as indicated at 94 which may be central processing units, input-output devices or the like. Many designers have a cell library consisting of standardized cells that perform desired logical operations, and which may be combined with other cells to form an integrated circuit having the desired functionality. A typical integrated circuit further comprises a large number of smaller devices such as logic gates 96 which are arranged in a generally rectangular pattern in the areas of the substrate 95 that are not occupied by macroblocks.
The logic gates 96 have terminals 98 to provide interconnections to other gates 96 on the substrate 95. Interconnections are made via vertical electrical conductors 97 and horizontal electrical conductors 99 that extend between the terminals 98 of the gates 96 in such a manner as to achieve the interconnections required by the netlist of the integrated circuit 93. It will be noted that only a few of the elements 96, 98, 97 and 99 are designated by reference numerals for clarity of illustration.
In conventional integrated circuit design, the electrical conductors 97 and 99 are formed in vertical and horizontal routing channels (not designated) in a rectilinear (Manhattan) pattern. Thus, only two directions for interconnect rouging are provided, although several layers of conductors extending in the two orthogonal directions may be provided to increase the space available for routing.
A goal of routing is to minimize the total wirelength of the interconnects, and also to minimize routing congestion. Achievement of this goal is restricted using conventional rectilinear routing because diagonal connections are not possible. A diagonal path between two terminals is shorter than two rectilinear orthogonal paths that would be required to accomplish the same connection.
Another drawback of conventional rectilinear interconnect routing is its sensitivity to parasitic capacitance. Since many conductors run in the same direction in parallel with each other, adjacent conductors form parasitic capacitances that can create signal crosstalk and other undesirable effect.
Other patents exist which contain incidental references to hexagonal structures, but do not disclose the hexagonal architecture of the present invention. For example, U.S. Pat. No. 5,323,036 purports to disclose a power FET transistor that has gate segments arranged in a hexagonal lattice pattern in an effort to reduce channel resistance. U.S. Pat. No. 5,323,036 does not teach or suggest providing three metal layers in a hexagonal architecture as provided by the present invention. Significantly, that patent does not even recognize the problem of minimizing interconnection wire lengths and interlayer capacitance or "crosstalk."
U.S. Pat. No. 5,095,343 purports to disclose a VDMOS device having P-type regions forming PN junctions that intersect the surface of the wafer in a closed path forming a hexagon along the plane of the surface. Each source region is stated to be opposite the space between two source regions in the adjacent body region. This is said to provide each cell with a plurality of spaced channel regions. According to this patent, the disclosed VDMOS device has a reduced power density at which zero temperature coefficient occurs so that the device allegedly can tolerate a given power dissipation for a longer time before damage occurs. U.S. Pat. No. 5,095,343 may teach away from over-the-cell routing; the patent describes a metal connection to the gate electrode, and states that the gate bond pad overlies an area of the surface of the wafer that does not contain source/body cells. This patent does not teach or suggest providing three metal layers in a hexagonal architecture preferably employing over-the-cell routing, and does not recognize the problem of minimizing interconnection wire lengths and interlayer capacitance or "crosstalk."
U.S. Pat. No. 5,130,767 purports to disclose a high power MOSFET transistor that has a plurality of closely packed polygonal sources spaced from one another on one surface of a semiconductor wafer. The patent states that the polygonal source regions are preferably hexagonal in shape. A single drain electrode is formed on the opposite surface of the semiconductor wafer. An elongated gate electrode is formed on the first surface of the wafer and it crosses a plurality of the polygonal sources. When a suitable control voltage is applied to the gate, annular channels around the polygonal sources become conductive to permit majority carrier conduction from the source regions through the wafer to the drain electrode on the opposite surface of the wafer. U.S. Pat. No. 5,130,767 does not teach or suggest providing three metal layers in a hexagonal architecture, and does not recognize the problem of minimizing interconnection wire lengths and interlayer "crosstalk."
While in the past satisfactory results were obtained using rectangular architectures employing two layers of metal, those old techniques will not suffice for many new designs incorporating millions of transistors. As very large scale integration designs advance, and attempts are made to place more and more transistors on the same area of a semiconductor chip, improved architectures are needed to provide minimal area designs and better performance. The techniques and architectures used in the past leave considerable room for improvement.